1. Field of the Invention
Embodiments of the present invention relate to integrated circuit device packaging; more specifically, to an interposer substrate capable of reducing cross-talk between signal lines which is suitable for interconnecting integrated circuit chips to a printed circuit board or other substrate. Embodiments of the present inventions also provide a composite interposer and method for producing the composite interposer which may be placed between an integrated circuit and a printed circuit board.
2. Description of the Prior Art
An interposer is a structure used in the manufacture of single and multi-chip modules (SCMs or MCMs) to electrically connect one or more integrated circuit chips (ICs) to a printed circuit board or other substrate. The interposer provides power and ground connections between the board or substrate and the ICs. The interposer also provides signal paths between the IC chips and the board or substrate, and if desired, between different chips mounted on the interposer. An interposer thus provides a means of interconnecting signal, power, and ground lines between a substrate, an integrated circuit chip or chips, and ultimately a package containing the chip(s).
As the number of components in electronic devices increases and the size of the individual components decreases, there is an increase in the number and density of power, ground, and signal interconnections needed between individual ICs and the substrate to which the chips are connected. This means that the density of the interconnections which need to be included as part of an interposer also increases. However, problems arise in placing signal lines in close proximity to each other and to power supply lines when fabricating such an interposer. These problems include interference and cross-talk arising from coupling between the lines on a common layer or between signal lines on different signal layers, and capacitive coupling between the lines and the substrate which produces noise in the signals. In conjunction with the separation between the various lines, the dielectric constant of the substrate material thus plays an important role in reducing (or creating) these type of problems.
A patentability investigation was conducted to obtain the state of the art with respect to addressing these disadvantages of conventional approaches to packaging IC chips in MCMs, and the following U.S. Patents were discovered, all of which are incorporated herein by reference thereto: U.S. Pat. No. 5,404,044 to Booth et al.; U.S. Pat. No. 5,468,681 to Pasch; U.S. Pat. No. 5,558,928 to DiStefano et al.; U.S. Pat. No. 5,590,460 to DiStefano et al.; and U.S. Pat. No. 5,691,041 to Frakeny et al.
U.S. Pat. No. 5,404,044 to Booth et al discloses a method of fabricating a multi-layer integrated circuit interposer having at least one layer of polyimide with wiring patterns etched in metal on both its top and bottom surfaces. An adhesive layer is applied over the metal to cover both surfaces. Via holes are drilled through one adhesive layer surface and through the polyimide layer to the other adhesive surface. Metal is blanket sputtered to cover the adhesive surfaces, any exposed metal and via side walls. Conductive adhesive paste is screened onto both surfaces to at least partially fill the vias. Using the screened adhesive paste as a mask, the blanket metal is sub-etched away exposing the underlying adhesive layer.
U.S. Pat. No. 5,468,681 to Pasch discloses a preformed planar structure with through holes in registration with solder balls (pads) on chip(s) and substrate. Liquid flux selectively fills the through holes for delivery to the solder balls during soldering. The through holes aid in maintaining registration of the chip(s) and the substrate. The through holes are sized to establish a predetermined mechanical structure of solder joints formed by the solder balls when fused together. The preformed planar structure is disclosed has having a planar core and opposing planar faces. The core is taught to be formed by thermosetting organic resin, such as polyimide, or non-organic material, such as alumina, polished sapphire, beryllium oxide, aluminum or aluminum nitride. The planar faces of the preformed planar structure are formed of thermoplastic resin or thermosetting material, such as polyacetal, epoxy (epoxy resins) or polystyrene.
U.S. Pat. No. 5,558,928 to DiStefano et al discloses sheetlike interposers having preselected interconnect locations on both major surfaces and electrically conductive elements extending between interconnect locations on opposite surfaces. The interposer is taught as having a flowable dielectric material on its major surfaces except at its interconnect locations. Electrically conductive material on circuit panels, on the interposers, at their respective interconnect locations may be flowable. The circuit panels and interposers are stacked in a superposed relation so that each interposer is disposed between two circuit panels, with the major surfaces of the interposers and circuit panels confronting one another, and with interconnect locations on the confronting surfaces of the circuit panels and interposers being aligned with one another.
U.S. Pat. No. 5,590,460 also to DiStefano et al provides an interposer for making connections to electrical contacts on the surface of microelectronic elements such as a circuit panel, a semiconductor chip or other element having a contact-bearing surface. The interposer includes a body having a first major surface, such that the body defines horizontal directions parallel to the first major surface and vertical directions perpendicular to the first major surface. The interposer in U.S. Pat. No. 5, 590,460 to DiStefano et al is further taught as having a plurality of conductors in the body, such as via conductors extending in or through the body, and including contacts at the first major surface of the body electrically connected to the conductors. Each contact is disclosed as extending over the first surface of the body in generally radially outwardly fashion from a central axis which is perpendicular to the first surface. Each contact has a periphery remote from the central axis. The contacts are adapted to deform so that the periphery of each contact will expand generally radially outwardly, away from the axis in response to a force applied to the contact directed toward the body.
U.S. Pat. No. 5,691,041 to Frankeny et al teaches a planar interposer of flexible dielectric material having a multiplicity of vias or pads covered with dendrites, which vias or pads are distributed in a pattern substantially conforming to an electronic ball grid array device. A rigid cap with a planar surface is aligned to be substantially coplanar with the surface of the ball grid array device. U.S. Pat. No. 5,691,041 to Frankeny et al also teaches a means for aligning a pattern of balls on a surface of the ball grid array device with the planar interposer and with a pattern contact region on a board, and means for translating the rigid cap to compress the ball grid array device, the interposer, and the contact regions of the board adequately to cause dendrite penetration into the ball grid array device balls and the contact regions on the board.
Disadvantages of conventional approaches to packaging IC chips in MCMs arise from the method used to deliver power to the chips. This problem results because power lines are typically routed through the same substrate which is utilized to carry signals to and from the chip. The power feedthroughs will compete for space with the signal I/O lines. This will further increase the problems caused by densely packed signal traces. Another important disadvantage is that the thinness of the substrates used in traditional multichip modules results in the power feeds to the IC chips having a relatively high impedance. This results in undesired noise, power loss, and excess thermal energy production. These problems are relevant to the routing of both power and signal lines though an interposer substrate.
Therefore, what is desired and what has been invented is a composite interposer for interconnecting a single integrated circuit chip to a substrate, or for interconnecting a plurality of chips to each other and to a substrate, which addresses the inherent and noted disadvantages of conventional structures. What is further needed and what has been invented is a method for fabricating a composite interposer.
Embodiments of the present invention are directed to an interposer for providing power, ground, and signal connections between an integrated circuit chip or chips and a substrate. The interposer includes a signal core and external power/ground connection wrap. The two sections may be fabricated and tested separately, then joined together using z-connection technology. The signal core is formed from a conductive power/ground plane positioned between two dielectric layers. A patterned metal layer is formed on each dielectric layer. The two metal layers are interconnected by a through via or post process. The conductive power/ground plane functions to reduce signal cross-talk between signal lines formed on the two patterned metal layers.
The power/ground wrap includes an upper substrate positioned above the signal core and a lower substrate positioned below the signal core. The upper and lower substrates of the power/ground wrap are formed from a dielectric film having a patterned metal layer on both sides, with the patterned layers connected by a through via or post process. The two power/ground wrap substrates may be formed separately or from one substrate which is bent into a desired form (e.g., a xe2x80x9cUxe2x80x9d shape). The two power/ground substrates are maintained in their proper alignment relative to the signal core and to each other by edge connectors which are also connected to the signal core""s intermediary power/ground plane.
The top layer of the upper power/ground wrap substrate and the bottom layer of the lower power/ground wrap substrate serve as the ground layer. The ground layer includes isolated pads for signal and power interconnections between the base substrate on which the interposer is mounted and the chip(s) mounted on top of the interposer. The bottom layer of the upper substrate and the top layer of the lower substrate of the power/ground wrap serve as the power layer and include isolated pads for signal interconnections. With an integrated circuit chip or chips connected to the upper layer of the top substrate of the power/ground wrap and a printed circuit board or other mounting substrate connected to the bottom layer of the lower substrate of the wrap, the inventive interposer provides a set of high density and electrically isolated signal, power, and ground interconnections having reduced cross-talk between signal lines.
Embodiments of the present invention are further directed to a method for fabricating a composite interposer comprising disposing a silicon layer on a substrate; selectively etching the silicon layer down to the substrate to develop silicon openings with a silicon profile, and to expose part of the substrate; and forming vias through the exposed part of the substrate. The method for fabricating further includes filling the vias and the silicon openings with a filler material (e.g., high-aspect-ratio-capable photodefinable epoxy) to form filled silicon openings and filled vias; forming first openings through the filled silicon openings and through the filled vias; and forming second openings through filler material to expose semiconductor devices on the silicon layer. The method further comprises interconnecting electrically, through the first openings and through the second openings, the exposed semiconductor devices with pads disposed against a bottom of the substrate. Each of the pads is selected from the group of pads consisting of voltage pads, ground pads, and signal pads. Selectively etching the silicon layer down to the substrate additionally includes forming a plurality of spaced silicon layers supported by the substrate. The first openings may be filled with a dielectric filler after interconnecting electrically the exposed semiconductor devices with the pads. The filler material may include an aspect ratio ranging from about 2:1 to about 40:1.
In one embodiment of the present invention a method is provided for fabricating a composite interposer comprising disposing a plurality of conductive elements (e.g., devices including semiconductive devices, metal pads, etc.) on a top of a silicon layer, leaving part of a top of the silicon layer exposed; disposing a dielectric material over the conductive elements and the exposed top of the silicon layer; and selectively removing dielectric material from over the conductive elements. Voltage or power planes and ground planes may then be formed. The method for fabricating a composite interposer additionally comprises selectively removing silicon from a bottom of the silicon layer to form silicon openings and to expose part of the dielectric material; filling the silicon openings with a polymer filler, leaving a polymer filler layer on the bottom of the silicon layer; securing a substrate to the polymer filler layer; and forming vias through the substrate, the polymer filler and the dielectric material. The vias may then be metal plated. The method additionally comprises testing the silicon layer including the conductive elements to determine if any of the conductive elements are defective. The forming of a voltage plane includes depositing a metal voltage layer on the dielectric material and coupling same to the exposed conductive elements. The forming of a ground plane comprises forming a plurality of vias in the second dielectric layer to produce a residual second dielectric layer and to re-expose the exposed metal-filled conductive elements; and depositing a metal ground metal on the residual second dielectric layer and in the vias in the second dielectric layer to couple the metal-filled conductive elements to the metal ground metal. A portion of the metal ground layer may be removed to produce an exposed second dielectric layer. Forming the vias includes forming vias through the produced exposed second dielectric layer. The plated vias may be filled and capped. The conductive element may be a metal pad or a semiconductor device (e.g., a capacitor).
In another embodiment of the present invention, a method is provided for fabricating a composite interposer disposing a plurality of conductive elements (e.g., devices including semiconductive devices, metal pads, etc.) on top of a silicon layer, leaving part of a top of the silicon layer exposed; disposing a dielectric material over the conductive elements and the exposed top of the silicon layer; and selectively removing silicon from a bottom of the silicon layer to form silicon openings and to expose part of the dielectric material. The method for fabricating a composite interposer additionally comprises filling the silicon openings with a polymer filler, leaving a polymer filler layer on the bottom of the silicon layer; securing a substrate to the polymer filler layer; selectively removing dielectric material from over the conductive elements; and forming vias through the substrate, the polymer filler, and the dielectric material. The vias may then be metal plated. The conductive elements may be tested for defectiveness.
These provisions together with the various ancillary provisions and features which will become apparent to those skilled in the art as the following description proceeds, are attained by the methods and composite interposer of the present invention, preferred embodiments thereof being shown with reference to the accompanying drawings, by way of example only, wherein: